Computers may comprise various types of memory for storing data. Each of these types of memory has various advantages that suit different applications. Flash memory, for example, is a solid state device used for fast and efficient memory storage. Examples of flash memory comprise a computer's BIOS chip, a memory stick, compact flash cards, SmartMedia™ cards and PCMCIA memory cards.
High-speed programming and erasing capabilities, low cost, ease of memory expansion, long lifespan and a file memory architecture make NAND Flash memory particularly useful in data-centric applications. NAND Flash memory has an input-output (“I/O”) interface and uses a protocol that includes fast read/write/erase commands, addresses and data. Despite the advantages, NAND Flash memory does not permit easy access to a random memory address. NAND Flash memory also may be prone to low reliability due to random errors generated by physical effects in the geometry of the NAND gates in the memory. Such random errors also may be caused by an excessive number of read, write and erase cycles.
To correct such errors, a host processor may use a NAND Flash controller (“controller”) to generate an error correction code (“ECC”). For the purposes of error checking and correction, an ECC may be generated when programming a NAND Flash with a particular data. Another ECC may be generated when reading the particular data from the NAND Flash. The two ECCs subsequently may be compared to locate and correct any differences which may represent errors caused by the NAND Flash memory.
Because NAND Flash memory typically is accessed in blocks of data, the controller may be forced to wait until a full block of data has been accessed before computing the ECC, thereby incurring a penalty in performance. Additionally, because a controller may have a limited number of registers in which to store completed ECC computations, the controller may pause several times to dump the contents of the register(s) to clear register space for new, completed ECC computations, resulting in further performance penalties. A method to compute and store the ECC without suffering a loss in performance is desirable.